First Demonstration of Novel Vertical Gate-All-Around Field-Effect-Transistors Featured by Self-Aligned and Replaced High-κ Metal Gates-Reference-Cited by-同舟云学术

First Demonstration of Novel Vertical Gate-All-Around Field-Effect-Transistors Featured by Self-Aligned and Replaced High-κ Metal Gates

Published:2021-05-26 Issue:11 Volume:21 Page:4730-4737
ISSN:1530-6984
Container-title:Nano Letters
language:en
Short-container-title:Nano Lett.

Author:

Li Chen¹²^ORCID,Zhu Huilong¹²³^ORCID,Zhang Yongkui¹,Wang Qi¹,Yin Xiaogen¹²,Li Junjie¹,Wang Guilei¹,Kong Zhenzhen¹,Ai Xuezheng¹,Xie Lu¹²,Liu Yongbo¹²,Li Yangyang¹²,Huang Weixing¹²,Yan Zijin¹²,Xiao Zhongrui¹²,Radamson Henry H.¹²,Li Junfeng¹,Wang Wenwu¹

Affiliation:

1. Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

2. University of Chinese Academy of Sciences, Beijing 100049, China

3. University of Science and Technology of China, Hefei, Anhui 230026, People’s Republic of China

Funder

the National Key Research and Development Program of China

the Youth Innovation Promotion Association of CAS

the National Natural Science Foundation of China

The Academy of Integrated Circuit of the Chinese Academy of Sciences

Publisher

American Chemical Society (ACS)

Subject

Mechanical Engineering,Condensed Matter Physics,General Materials Science,General Chemistry,Bioengineering

Link

https://pubs.acs.org/doi/pdf/10.1021/acs.nanolett.1c01033

Reference37 articles.

1. IEEE International Roadmap for Devices and Systems 2020 More Moore. https://irds.ieee.org/editions/2020/more-moore (accessed 2020-10-08).

2. Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around

3. Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond

4. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

5. Many-Tier Vertical GAAFET (V-FET) for Ultra-Miniaturized Standard Cell Designs Beyond 5 nm

Cited by 20 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Fully Printed Negative-Capacitance Field-Effect Transistors with Ultralow Subthreshold Swing and High Inverter Signal Gain;ACS Applied Materials & Interfaces;2024-07-16

2. A Common Source 3D FeFET with Disturb Inhibition Program and Erase Method;ECS Journal of Solid State Science and Technology;2024-06-03

3. Virtual Fab Coupled Physics-Based Simulation Design of Sub-2nm Node 3D Heterogeneous Si/IGZO 6T SRAM;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10

4. CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology;Nanomaterials;2024-05-09

5. High performance junctionless FDSOI SiGe channel p-FinFET with high ION/IOFF ratio and excellent SS;Materials Science in Semiconductor Processing;2024-03