Virtual Fab Coupled Physics-Based Simulation Design of Sub-2nm Node 3D Heterogeneous Si/IGZO 6T SRAM
Author:
Affiliation:
1. Institute of Microelectronics, Chinese Academy of Sciences,Beijing,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10616249/10617469/10617609.pdf?arnumber=10617609
Reference10 articles.
1. The Complementary FET (CFET) for CMOS scaling beyond N3
2. Vertical Sandwich Gate-All-Around Field-Effect Transistors With Self-Aligned High-k Metal Gates and Small Effective-Gate-Length Variation
3. First Demonstration of Novel Vertical Gate-All-Around Field-Effect-Transistors Featured by Self-Aligned and Replaced High-κ Metal Gates
4. Vertical Channel-All-Around (CAA) IGZO FET under 50 nm CD with High Read Current of 32.8 μA/μm (Vth + 1 V), Well-performed Thermal Stability up to 120 ℃ for Low Latency, High-density 2T0C 3D DRAM Application
5. Accurate Simulation of Transistor-Level Variability for the Purposes of TCAD-Based Device-Technology Cooptimization
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