Assessing Ultrathin Wafer-Scale WS<sub>2</sub> as a Diffusion Barrier for Cu Interconnects-Reference-Cited by-同舟云学术

Assessing Ultrathin Wafer-Scale WS₂ as a Diffusion Barrier for Cu Interconnects

Published:2023-09-05 Issue:9 Volume:5 Page:5074-5081
ISSN:2637-6113
Container-title:ACS Applied Electronic Materials
language:en
Short-container-title:ACS Appl. Electron. Mater.

Author:

El Kazzi Salim¹²,Lum Ya Woon¹²,Erofeev Ivan¹²,Vajandar Saumitra¹,Pasko Sergej³,Krotkus Simonas³,Conran Ben³,Whear Oliver³,Osipowicz Thomas¹,Mirsaidov Utkur¹²⁴⁵^ORCID

Affiliation:

1. Department of Physics, National University of Singapore, 117551 Singapore, Singapore

2. Centre for BioImaging Sciences, Department of Biological Sciences, National University of Singapore, 117557 Singapore, Singapore

3. AIXTRON SE, Herzogenrath 52134, Germany

4. Centre for Advanced 2D Materials, National University of Singapore, 117546 Singapore, Singapore

5. Department of Materials Science and Engineering, National University of Singapore, 117575 Singapore, Singapore

Funder

Agency for Science, Technology and Research

National Research Foundation Singapore

Publisher

American Chemical Society (ACS)

Subject

Materials Chemistry,Electrochemistry,Electronic, Optical and Magnetic Materials

Link

https://pubs.acs.org/doi/pdf/10.1021/acsaelm.3c00809

Reference37 articles.

1. High-performance interconnects: an integration overview

2. Resistivity dominated by surface scattering in sub-50 nm Cu wires

3. PVD- Treated ALD TaN for Cu Interconnect Extension to 5nm Node and Beyond

4. More Moore. International Roadmap for Devices and Systems; Institute of Electrical and Electronics Engineers, 2020. https://irds.ieee.org/ (accessed Feb 12, 2022).

5. Erratum: Self-Assembled Nano-Stufﬁng Structure in CVD and ALD Co(W) Films as a Single-Layered Barrier/Liner for Future Cu-Interconnects [ECS J. Solid State Sci. Technol.,2, P471 (2013)]

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