Copper Electroplating for Damascene ULSI Interconnects

Abstract

ABSTRACTCopper was electroplated on sputtered Cu seed layer with Ta diffusion barrier. We achieved enhanced Cu deposition at the bottom of trenches/vias and defect-free filling sub-0.5 μm trenches (down to 0.25 μm width) of high aspect ratio (up to 4:1). Large grains occupying the entire trench were observed. Bottom step coverage of electroplated copper in sub-0.5 μm trenches was estimated to be about 140%, while sidewalls step coverage was about 120%. Via resistance for sub-0.5 μm vias was measured to be below 0.55 Ω. Strong <111> texture, large grains, and low tensile stress were observed in electroplated Cu films and in-laid Cu lines after low temperature anneal.