Affiliation:
1. School of Electronic and Electrical Engineering, Kyungpook National University, Daegu 702-201, Republic of Korea
Abstract
In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM), based on polycrystalline silicon (poly-Si) nanotube structure with a grain boundary (GB), is designed and analyzed using technology computer-aided design (TCAD) simulation. In the proposed 1T-DRAM, the 1T-DRAM cell exhibited a sensing margin of 422 μA/μm and a retention time of 213 ms at T = 358 K with a single GB. To investigate the effect of random GBs, it was assumed that the number of GB is seven, and the memory characteristics depending on the location and number of GBs were analyzed. The memory performance rapidly degraded due to Shockley–Read–Hall recombination depending on the location and number of GBs. In the worst case, when the number of GB is 7, the mean of the sensing margin was 194 µA/µm, and the mean of the retention time was 50.4 ms. Compared to a single GB, the mean of the sensing margin and the retention time decreased by 59.7% and 77.4%, respectively.
Funder
National Research Foundation of Korea
Ministry of Education
Basic Science Research Program
National R&D Program
Semiconductor Industry Collaborative Project
IC Design Education Center
Subject
General Materials Science,General Chemical Engineering
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