Statistical Analysis of Increased Immunity to Poly-Si Grain Boundaries in Nanosheet CMOS Logic Inverter Through Sheet Stacking-Reference-Cited by-同舟云学术

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Statistical Analysis of Increased Immunity to Poly-Si Grain Boundaries in Nanosheet CMOS Logic Inverter Through Sheet Stacking

Published:2024-08-27 Issue: Volume: Page:
ISSN:1876-990X
Container-title:Silicon
language:en
Short-container-title:Silicon

Author:

Kim Min Seok,Lee Sang Ho,Park Jin,Jeon So Ra,Bae Seung Ji,Hong Jeong Woo,Jang Jaewon,Bae Jin-Hyuk,Yoon Young Jun,Kang In Man

Funder

National Research Foundation of Korea

BK21 FOUR project

IC Design Education Center

Publisher

Springer Science and Business Media LLC

Link

https://link.springer.com/content/pdf/10.1007/s12633-024-03113-6.pdf

Reference25 articles.

1. Bangsaruntip S et al (2013) Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond. IEDM Tech Dig 20(2):1–20

2. Sung P-J et al (2020) Fabrication of vertically stacked nanosheet junctionless field-effect transistors and applications for the CMOS and CFET inverters. IEEE Trans Electr Dev 67(9):3504–3509

3. Kim S et al (2020) Investigation of electrical characteristic behavior induced by channel-release process in stacked nanosheet gate-all-around MOSFETs. IEEE Trans Electron Devices 67(6):2648–2652

4. Jung S-G, Kim J-K, Hyun-Yong Yu (2022) Analytical model of contact resistance in vertically stacked nanosheet FETs for sub-3-nm technology node. IEEE Trans Electron Devices 69(3):930–935

5. Yoon J-S, Baek R-H (2020) Device design guideline of 5-nm-node FinFETs and nanosheet FETs for analog/RF applications. IEEE Access 8:189395–189403

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