Analytical Model of Contact Resistance in Vertically Stacked Nanosheet FETs for Sub-3-nm Technology Node-Reference-Cited by-同舟云学术

Analytical Model of Contact Resistance in Vertically Stacked Nanosheet FETs for Sub-3-nm Technology Node

Published:2022-03 Issue:3 Volume:69 Page:930-935
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Jung Seung-Geun¹^ORCID,Kim Jeong-Kyu²,Yu Hyun-Yong¹^ORCID

Affiliation:

1. School of Electrical Engineering, Korea University, Seoul, South Korea

2. Department of Electrical Engineering, Stanford University, Stanford, CA, USA

Funder

Research Project of Samsung Electronics Company Ltd.

National Research Foundation of Korea

Ministry of Science and ICT for Original Technology Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/9722602/09696164.pdf?arnumber=9696164

Reference37 articles.

1. Influence of the Schottky barrier height on the silicon solar cells

2. Modeling source/drain contact resistance in nanoscale MOSFETs;chen;Proc SISPAD,2012

3. Contact module engineering for advanced CMOS technologies: Key concepts, engineering techniques and device integration challenges;breil;Proc Symp VLSI Technol,2021

4. Analysis of current crowding in thin film contacts from exact field solution

5. Titanium Silicide on Si:P With Precontact Amorphization Implantation Treatment: Contact Resistivity Approaching $1 \times 10^{-9}$ Ohm-cm2

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