Compact Modeling of Advanced Gate-All-Around Nanosheet FETs Using Artificial Neural Network
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Published:2024-01-31
Issue:2
Volume:15
Page:218
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ISSN:2072-666X
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Container-title:Micromachines
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language:en
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Short-container-title:Micromachines
Author:
Zhao Yage1ORCID, Xu Zhongshan1, Tang Huawei1, Zhao Yusi1, Tang Peishun1ORCID, Ding Rongzheng1, Zhu Xiaona1, Zhang David Wei12, Yu Shaofeng12
Affiliation:
1. School of Microelectronics, Fudan University, Shanghai 200433, China 2. National Integrated Circuit Innovation Center, Shanghai 201203, China
Abstract
As the architecture of logic devices is evolving towards gate-all-around (GAA) structure, research efforts on advanced transistors are increasingly desired. In order to rapidly perform accurate compact modeling for these ultra-scaled transistors with the capability to cover dimensional variations, neural networks are considered. In this paper, a compact model generation methodology based on artificial neural network (ANN) is developed for GAA nanosheet FETs (NSFETs) at advanced technology nodes. The DC and AC characteristics of GAA NSFETs with various physical gate lengths (Lg), nanosheet widths (Wsh) and thicknesses (Tsh), as well as different gate voltages (Vgs) and drain voltages (Vds) are obtained through TCAD simulations. Subsequently, a high-precision ANN model architecture is evaluated. A systematical study on the impacts of ANN size, activation function, learning rate, and epoch (the times of complete pass through the entire training dataset) on the accuracy of ANN models is conducted, and a shallow neural network configuration for generating optimal ANN models is proposed. The results clearly show that the optimized ANN model can reproduce the DC and AC characteristics of NSFETs very accurately with a fitting error (MSE) of 0.01.
Funder
platform for the development of next generation integrated circuit technology Shanghai Sailing Program
Subject
Electrical and Electronic Engineering,Mechanical Engineering,Control and Systems Engineering
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