Dead Zone Minimization Using Variable-Delay Element in CP-PLL for 5G Applications

Abstract

The deadzone occurring in a phase-frequency detector (PFD) is a critical parameter that affects the performance of a phase-locked loop (PLL). Though a fixed-delay element reduces the deadzone, it creates an imbalance in the pulse-arrival time and among the up and down signals to the charge pump, which increases the phase noise in the output spectrum of the PLL. Therefore, in this work a new variable-delay element (VDE) is incorporated in the PFD to reduce the dead zone and consequently the phase noise of the PLL. The performance of the proposed PFD incorporated in PLL is analyzed using cadence virtuoso 90 nm CMOS technology, achieving a phase noise of −148.89 dBc/Hz at a frequency offset of 1 MHz, a lock time of 6.01 us, a power of 0.056 mW, and a dead zone of 110.5 ps, while operating at 3.5 GHz of frequency, making it suitable for 5G applications.