A Calibrated Phase/Frequency Detector for Reference Spur Reduction in Charge-Pump PLLs-Reference-Cited by-同舟云学术

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A Calibrated Phase/Frequency Detector for Reference Spur Reduction in Charge-Pump PLLs

Published:2006-09 Issue:9 Volume:53 Page:822-826
ISSN:1057-7130
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Charles C.T.,Allstot D.J.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Signal Processing

Link

http://xplorestaging.ieee.org/ielx5/8920/35981/01705047.pdf?arnumber=1705047

Cited by 35 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. A Wideband and Low Reference Spur PLL with Clock Feedthrough Suppressed and Low Current Mismatch Charge Pump and Symmetrical CML Divider;Electronics;2023-10-07

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4. Design of PFD with free dead zone and minimized blind zone for high speed PLL application;International Journal of Electronics;2022-09-09

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