A Simple Doping Process Achieved by Modifying the Passivation Layer for Self-Aligned Top-Gate In-Ga-Zn-O Thin-Film Transistors at 200 °C

Abstract

In this paper, a facile modifying technique of source/drain regions conductivity was proposed for self-aligned top-gate In-Ga-Zn-O (IGZO) thin-film transistors (TFTs) by controlling the process parameter of the passivation layer at relatively low temperatures. The sheet resistance of the source and drain regions of IGZO was approximately 365 Ω/□, and there was no significant change within a month. The device parameters of mobility, threshold voltage, subthreshold swing, and current switching ratio of the fabricated device were 15.15 cm2V−1s−1, 0.09 V, 0.15 V/dec, and higher than 109, respectively. The threshold voltage drift under negative bias illumination stress was −0.34 V. In addition, a lower channel width-normalized contact resistance of 9.86 Ω·cm was obtained.