Analysis and Construction of Hardware Accelerators for Calculating the Shortest Path in Real-Time Robot Route Planning
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Published:2024-06-02
Issue:11
Volume:13
Page:2167
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ISSN:2079-9292
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Container-title:Electronics
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language:en
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Short-container-title:Electronics
Author:
Esteves Linton Thiago Costa1ORCID, Oliveira Wagner Luiz Alvez de2ORCID, Farias Paulo César Machado de Abreu2ORCID
Affiliation:
1. Instituto Federal Baiano, Salvador 41720-052, Brazil 2. Department of Electrical and Computer Engineering, Federal University of Bahia, Salvador 40210-910, Brazil
Abstract
This study introduces an optimization approach for calculating the shortest path in mobile robot route planning. The proposed solution targets real-time processing requirements by offering a high-performance alternative. This is achieved by embedding in the dedicated hardware an architecture which emphasizes parallelism. Through improvements in parallel exploration techniques, our solution aims to present not only a boost in performance but also a dynamic adaptation to graph changes, accommodating randomly occurring edge insertions or deletions as environmental conditions fluctuate. We present the developed architecture alongside its results. Our method efficiently updates obstacle matrices, resulting in a remarkable 120-fold improvement for 1024-node graphs. When utilizing a cost-effective device like the Cyclone IV E, it achieves approximately 12 times the performance of software applications.
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