A 3GS/s 12-bit Current-Steering Digital-to-Analog Converter (DAC) in 55 nm CMOS Technology

Abstract

A 3GS/s 12-bit current-steering digital-to-analog converter (DAC) fabricated in 55 nm complementary metal–oxide–semiconductor (CMOS) technology has been presented. A partial randomization dynamic element matching (PRDEM) method based on switching sequence optimization is proposed to mitigate the mismatch effect and suppress the harmonic distortion with low hardware complexity. In the switching current cell, the cascode structure together with “always-ON” small current sources are used to keep the output impedance high and uniform. A compact layout of the switching current array is carefully designed, featuring short wires routing and small parasitic capacitance. According to the measured results at 3GS/s, this DAC demonstrates a spurious-free dynamic range (SFDR) of 74.64 dBc at low frequency and 50 dBc at 1.5 GHz output. The chip occupies an active area of 0.2 × 0.48 mm2 and consumes a total power of 495 mW.