A 6-bit 2.4 GS/s Potentiometric DAC using 150nm CMOS Technology

Author:

Chatterjee Souvik1,. Hasanujjaman1

Affiliation:

1. Maulana Abul Kalam Azad University of Technology, West Bengal

Abstract

Abstract

In order to meet the demands of modern applications, we require a high-frequency digital to analog converter (DAC) circuit that can function with high precision, high speed, and low power. A 6-bit DIGITAL TOANALOGCONVERTER(DAC) using PASSTRANSISTOR logic using .15um CMOS Technology is presented in this paper to linearity, analyze accuracywith highfrequency clk input.Integral nonlinearity needs to be smaller than for correct DAC operation. In this work, a 6-bit DAC format with a switch based on PASSS TRANSISTOR logic and .015um CMOS technology is introduced. The suggested design is simulated using the TANNER EDA tool.The proposed DAC is simulated in .15um CMOS technology with 5volt of supply voltage. The average power consumption of the designed DAC is 19.41mw with the sample rate of 2.4 GS/s

Publisher

Research Square Platform LLC

Reference22 articles.

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4. A.Narayanan, M., Bengtsson, R., Ragavan, Duong, Q.-T.: A 0.35µm CMOS 6-bit current steering DAC, 2013 European Conference on Circuit Theory and Design (ECCTD), Dresden, Germany, pp. 1–4, (2013). 10.1109/ECCTD.2013.6662280

5. A 3GS/s 12-bit Current-Steering Digital-to-Analog Converter (DAC) in 55 nm CMOS Technology;Wang D;Electronics,2019

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