A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS

Author:

Zheng Yan,Ye Fan,Ren Junyan

Abstract

This paper presents a 12-bit, 100 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) based on a bridge capacitor array with redundancy and non-linearity calibration. The differential non-linearity calibration method was proposed to compensate for the linearity, which is degraded by the parasitic capacitance of the bridge capacitor. To reduce the power dissipation and alleviate the settling error of the DAC capacitor array, a hybrid redundant scheme was proposed. A low-power, high-performance SAR ADC was implemented based on the proposed techniques. This SAR ADC prototype was implemented in 28 nm CMOS technology. Measurement results showed that the proposed SAR ADC could achieve a (signal-to-noise distortion ratio) SNDR of 61.46 dB and 58.82 dB at low and Nyquist input frequencies, respectively, resulting in figure of merits (FOMs) of 8.69 fJ/conversion and 11.8 fJ/conversion step, respectively. The SAR ADC core occupied an active area 0.0227 mm2.

Funder

Ministry of Science and Technology of the People's Republic of China

Publisher

MDPI AG

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering

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1. A 12-bit 50MS/s SAR ADC with non-binary split capacitive DAC in 40nm CMOS;IEICE Electronics Express;2024-08-25

2. Design and Simulation of 1 0- Bit SAR ADC Using 18nm FinFET Technology;2024 IEEE 14th Symposium on Computer Applications & Industrial Electronics (ISCAIE);2024-05-24

3. Power-up Self Auto Calibration of High Speed SAR Converter in a 22nm FD-SOI CMOS Process;2024 IEEE 42nd VLSI Test Symposium (VTS);2024-04-22

4. A High ENOB 14-Bit ADC without Calibration;Electronics;2024-01-31

5. A Cryogenic 8-Bit 32 MS/s SAR ADC Operating down to 4.2 K;Electronics;2023-03-16

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