A 12-bit 50MS/s SAR ADC with non-binary split capacitive DAC in 40nm CMOS-Reference-Cited by-同舟云学术

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A 12-bit 50MS/s SAR ADC with non-binary split capacitive DAC in 40nm CMOS

Published:2024-08-25 Issue:16 Volume:21 Page:20240311-20240311
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Hou Xueshi¹,Duan Zongming¹²,Huang Zhixiang¹²,Wu Bowen³,Zhao Dixian⁴,Feng Jian¹²,Fang Ming¹²

Affiliation:

1. School of Electronics and Information Engineering, Anhui University

2. Anhui University, the Information Materials and Intelligent Sensing Laboratory of Anhui Province, Center for Big Data and Population Health of IHM

3. East China Research Institute of Electronic Engineering

4. Southeast University School of Information Science and Engineering

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Link

https://www.jstage.jst.go.jp/article/elex/21/16/21_21.20240311/_pdf

Reference31 articles.

1. [1] D. Luu, et al.: “A 12-bit 300-MS/s SAR ADC with inverter-based preamplifier and common-mode regulation DAC in 14-nm CMOS FinFET,” IEEE J. Solid-State Circuits 53 (2018) 3268 (DOI: 10.1109/JSSC.2018.2862890).

2. [2] J. Luo, et al.: “A 0.9-V 12-bit 100-MS/s 14.6-fJ/conversion-step SAR ADC in 40-nm CMOS,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 26 (2018) 1980 (DOI: 10.1109/TVLSI.2018.2846746).

3. [3] L. Scaletti, et al., “A 10.2-ENOB, 150-MS/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters,” NEWCAS (2022) 978 (DOI: 10.1109/NEWCAS52662.2022.9842195).

4. [4] Y. Zhao, et al.: “A 0.55V 10-bit 100-MS/s SAR ADC with 3.6-fJ/conversion-step in 28nm CMOS for RF receivers,” IEEE Trans. Circuits Syst. II, Exp. Briefs 70 (2023) 1811 (DOI: 10.1109/TCSII.2021.3117941).

5. [5] G. Zanoletti, et al.: “A 250-MS/s 9.9ENOB 80.7dB-SFDR top-plate input SAR ADC with charge linerization,” IIEEE Trans. Circuits Syst. II, Exp. Briefs 71 (2024) 1551 (DOI: 10.1109/TCSII.2023.3336943).

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