Two novel low power and very high speed pulse triggered flip-flops

Author:

Razmdideh Ramin1,Saneei Mohsen2

Affiliation:

1. Graduate University of Advanced Technology; Kerman Iran

2. Shahid Bahonar University of Kerman; Kerman Iran

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Reference19 articles.

1. A low power static dual edge-triggered flip-flop using an output-controlled discharge configuration;Phyu;International Symposium on Circuits and Systems,2005

2. Pre-capturing static pulsed flip-flops;Ghadiri;International Symposium on Circuits and Systems,2005

3. Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops;Phyu;IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2011

4. Activity-Sensitive flip-flop and latch selection for reduced energy;Heo;IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2007

5. Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop;Liu;International Symposium on Circuits and Systems,2006

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2. Design and Analysis of 18T Master-Slave Flip-Flop Circuit;2023 12th International Conference on System Modeling & Advancement in Research Trends (SMART);2023-12-22

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4. Static Single Phase Contention Pulsed Latch for Low Voltage Operation;VLSI, Communication and Signal Processing;2023

5. Design of Low Power N-Bridge Master and P-Bridge Slave Topologically Arranged Flip-Flop;2022 International Conference on Smart Generation Computing, Communication and Networking (SMART GENCON);2022-12-23

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