<scp>SiC</scp> ‐based analytical model for gate‐stack dual metal nanowire <scp>FET</scp> with enhanced analog performance-Reference-Cited by-同舟云学术

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SiC ‐based analytical model for gate‐stack dual metal nanowire FET with enhanced analog performance

Published:2022-02 Issue:4 Volume:35 Page:
ISSN:0894-3370
Container-title:International Journal of Numerical Modelling: Electronic Networks, Devices and Fields
language:en
Short-container-title:Int J Numerical Modelling

Author:

Neeraj ¹,Goel Anubha²^ORCID,Sharma Shobha¹,Rewari Sonam³,Gupta Radhey Shyam²

Affiliation:

1. Department of Electronics and Communication Engineering Indira Gandhi Delhi Technical University For Women Delhi India

2. Department of Electronics and Communication Engineering Maharaja Agrasen Institute Of Technology Delhi India

3. Department of Electronics and Communication Engineering Delhi Technological University Delhi India

Publisher

Wiley

Subject

Electrical and Electronic Engineering,Computer Science Applications,Modeling and Simulation

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1002/jnm.2986

Reference30 articles.

1. Performance analysis of asymmetric dielectric modulated dual short gate tunnel field effect transistor

2. RaskinJ.P.SOI technology pushes the limits of CMOS for RF applications. IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF);2016:17‐20.

3. Explicit Continuous Models for Double-Gate and Surrounding-Gate MOSFETs

4. NirmalD KumarPV JoyD JebalinBK KumarNM.Nanoscale tri‐gate MOSFET for ultra low power applications using high‐k dielectrics nanoelectronics. 5th IEEE International Conference (INEC).2013:12‐19.

5. Modeling of Nanoscale Gate-All-Around MOSFETs

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5. Improved analog and AC performance for high frequency linearity based applications using gate-stack dual metal (DM) nanowire (NW) FET (4H-SiC);Microsystem Technologies;2023-06-10

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