Cost reduction in bottom-up hierarchical-based VLSI floorplanning designs-Reference-Cited by-同舟云学术

Cost reduction in bottom-up hierarchical-based VLSI floorplanning designs

Published:2013-07-19 Issue:3 Volume:43 Page:286-306
ISSN:0098-9886
Container-title:International Journal of Circuit Theory and Applications
language:en
Short-container-title:Int. J. Circ. Theor. Appl.

Author:

Hoo Chyi-Shiang¹,Jeevan Kanesan¹,Ramiah Harikrishnan¹

Affiliation:

1. Department of Electrical Engineering; University of Malaya; Lembah Pantai 50603 Kuala Lumpur Malaysia

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Link

http://onlinelibrary.wiley.com/wol1/doi/10.1002/cta.1939/fullpdf

Reference67 articles.

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2. Computer-aided design and optimization of control units for VLSI processors;Micheli;International Journal of Circuit Theory and Applications,1988

3. Symmetry-aware placement algorithm using transitive closure graph representation for analog integrated circuit;Zhang;International Journal of Circuit Theory and Applications,2010

4. Interlaced switch boxed placement for three-dimensional FPGA architecture design;Hsu;International Journal of Circuit Theory and Applications,2010

5. Module Placement for Large Chips Based on Sparse Linear Equations;Tsay;International Journal of Circuit Theory and Applications,1988

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