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Module placement for large chips based on sparse linear equations

  • Published:1988-10 Issue:4 Volume:16 Page:411-423
  • ISSN:0098-9886
  • Container-title:International Journal of Circuit Theory and Applications
  • language:en
  • Short-container-title:Int. J. Circ. Theor. Appl.

Author:

Tsay Ren-Song,Kuh Ernest S.,Hsu Chi-Ping

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Reference13 articles.

1. Circuit layout

2. , , , and , ‘An effective hierarchical approach to high complexity circuit layout’, IEEE CICC, 1987, pp. 614–617.

3. Anr-Dimensional Quadratic Placement Algorithm

4. and , ‘Timber Wolf3.2: a new standard cell placement and global routing package’, Proc. 23rd DAC, 1986, pp. 432–439.

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1. Improved Wire Length-Driven Placement Technique for Minimizing Wire Length, Area and Timing;Journal of Low Power Electronics;2017-09-01

2. Cost reduction in bottom-up hierarchical-based VLSI floorplanning designs;International Journal of Circuit Theory and Applications;2013-07-19

3. A wire length estimation technique utilizing neighborhood density equations;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;1996

4. An efficient multilevel placement technique using hierarchical partitioning;IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications;1992-06

5. Adaptive cluster growth: a new algorithm for circuit placement in rectilinear regions;Computer-Aided Design;1992-01
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