Interlaced switch boxes placement for three-dimensional FPGA architecture design-Reference-Cited by-同舟云学术

Interlaced switch boxes placement for three-dimensional FPGA architecture design

Published:2010-11-04 Issue:5 Volume:40 Page:489-502
ISSN:0098-9886
Container-title:International Journal of Circuit Theory and Applications
language:en
Short-container-title:Int. J. Circ. Theor. Appl.

Author:

Hsu Chun-Lung,Huang Yu-Sheng,Lee Fong-Chao

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Link

http://onlinelibrary.wiley.com/wol1/doi/10.1002/cta.739/fullpdf

Reference28 articles.

1. Design of FPGA interconnect for multilevel metallization;DeHon;IEEE Transactions on VLSI Systems,2004

2. FPGA implementation of a coupled-map-lattice-based cryptosystem;Li;International Journal of Circuit Theory and Applications,2010

3. Digital architectures realizing piecewise-linear multivariate functions: two FPGA implementations;Marco;International Journal of Circuit Theory and Applications,2009

4. Siozios K Sotiriadis K Pavlidis VF Sondris D Exploring alternative 3D FPGA architectures: design methodology and CAD tool support 652 655

5. Wiring requirement and three-dimensional integration technology for field programmable gate arrays;Rahman;IEEE Transactions on VLSI Systems,2003

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