PDNOC: Partially diagonal network-on-chip for high efficiency multicore systems

Author:

Xu Thomas Canhao1,Leppänen Ville1,Liljeberg Pasi1,Plosila Juha1,Tenhunen Hannu1

Affiliation:

1. Department of Information Technology; University of Turku; Turku 20014 Finland

Publisher

Wiley

Subject

Computational Theory and Mathematics,Computer Networks and Communications,Computer Science Applications,Theoretical Computer Science,Software

Reference37 articles.

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2. Kumar S Jantsch A Soininen JP Forsell M Millberg M Oberg J Tiensyrja K Hemani A A network on chip architecture and design methodology IEEE Computer Society Annual Symposium on VLSI, 2002 Pittsburgh, PA 2002 105 112 10.1109/ISVLSI.2002.1016885

3. Networks on Chip

4. Optimal placement of vertical connections in 3d network-on-chip;Xu;Journal of Systems Architecture,2013

5. A study of 3d network-on-chip design for data parallel h.264 coding;Xu;Microprocessors and Microsystems,2011

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