Application of Logical Sub-networking in Congestion-aware Deadlock-free SDmesh Routing

Author:

Das Tuhin Subhra1,Ghosal Prasun1,Chatterjee Navonil2,Nath Arnab1,Banerjee Akash1,Khastagir Subhojyoti1

Affiliation:

1. Indian Institute of Engineering Science and Technology, Shibpur, India

2. Lab-STICC, Université Bretagne Sud

Abstract

An adaptive routing helps in evading early network saturation by steering data packets through the less congested area at the oppressive loaded situation. However, performances of adaptive routing are not always promising under all circumstances. Say for, given more freedom in choosing an alternate route on non-minimal paths for a substantially loaded network even may result in worsening network performances due to following longer route under adaptive routing. Here, underlying topology facilitates routing by offering more alternate short-cut routes on minimal or quasi-minimal paths. This work presents a congestion-aware (CA) adaptive routing for one-hop diagonally connected subnet-based mesh (SDmesh) network aiming to facilitate both performances and routing flexibility simultaneously. Our proposed technique on the selected system facilitates packet routing, offering more options in choosing an output link from minimal or quasi-minimal paths and hence helps in lowering packet delay by shortening the length of traversed traffic under the oppressive loaded situation. Furthermore, we have also employed a congestion-aware virtual input crossbar router aiming to split the entire network into two distinct logically separated sub-networks. It facilitates preserving important routing properties like deadlock, live-lock fairness, and other essential routing constraints. Experiments, conducted over two 8×8- and 12×12-sized networks, show an average improvement of 25--87.5% saturated latency and 60--83% throughput improvement under uniform traffic patterns for the proposed CA routing compared to centralized adaptive XY routing. Experimental results on application-specific PARSEC and SPLASH2 benchmark suites show an average of 22--50% latency and 23--30% throughput improvements by the proposed technique compared to centralized XY routing on the baseline mesh network. Moreover, experiments were also carried out to check the performance of the proposed routing method with different newly proposed deadlock-free adaptive routing approaches over the same subnet-based diagonal mesh (SDmesh) network and reported.

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Software

Reference37 articles.

1. Network-on-chip architectures and design methods;Benini L.;IEE Proc. Comput. Dig. Techn.,2005

2. Performance evaluation of many-core systems: Case study with TILEPro64;Kim Han-Yee;IET Comput. Dig. Techn.,2013

3. 2011. International Technology Roadmap for Semiconductors. Online. Retrieved from http://www.itrs2.net/itrs-reports.html. 2011. International Technology Roadmap for Semiconductors. Online. Retrieved from http://www.itrs2.net/itrs-reports.html.

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

同舟云学术

1.学者识别学者识别

2.学术分析学术分析

3.人才评估人才评估

"同舟云学术"是以全球学者为主线,采集、加工和组织学术论文而形成的新型学术文献查询和分析系统,可以对全球学者进行文献检索和人才价值评估。用户可以通过关注某些学科领域的顶尖人物而持续追踪该领域的学科进展和研究前沿。经过近期的数据扩容,当前同舟云学术共收录了国内外主流学术期刊6万余种,收集的期刊论文及会议论文总量共计约1.5亿篇,并以每天添加12000余篇中外论文的速度递增。我们也可以为用户提供个性化、定制化的学者数据。欢迎来电咨询!咨询电话:010-8811{复制后删除}0370

www.globalauthorid.com

TOP

Copyright © 2019-2024 北京同舟云网络信息技术有限公司
京公网安备11010802033243号  京ICP备18003416号-3