Design and evaluation of an energy efficient DiamondMesh topology for on-chip interconnection networks-Reference-Cited by-同舟云学术

Design and evaluation of an energy efficient DiamondMesh topology for on-chip interconnection networks

Published:2022-12 Issue:3-4 Volume:26 Page:161-187
ISSN:0929-5585
Container-title:Design Automation for Embedded Systems
language:en
Short-container-title:Des Autom Embed Syst

Author:

Varanasi Lakshmi Kiranmai,Srinivasarao B. K. N

Publisher

Springer Science and Business Media LLC

Subject

Hardware and Architecture,Software

Link

https://link.springer.com/content/pdf/10.1007/s10617-022-09266-0.pdf

Reference26 articles.

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2. Kundu S, Chattopadhyay S (2014) Network-on-chip: the next generation of system-on-chip integration CRC Press. Tayor and Francis group, UK

3. Kumar SA et al (2002) A network on chip architecture and design methodology. In: Proceedings IEEE computer society annual symposium on VLSI. New Paradigms for VLSI Systems Design, ISVLSI

4. Wang C, Hu W-H, Lee SE, Bagherzadeh N (2011) Area and power-efficient innovative congestion-aware network-on-chip architecture. J Syst Archit 57(1):24–38. https://doi.org/10.1016/j.sysarc.2010.10.009

5. Gupta GK, Jha SK (2021) Formation of fault and balanced ring for fault tolerance in Dmesh network. J Instit Eng India: Series B 102(5):979–985

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