Area and power-efficient innovative congestion-aware Network-on-Chip architecture

Author:

Wang Chifeng,Hu Wen-Hsiang,Lee Seung Eun,Bagherzadeh Nader

Publisher

Elsevier BV

Subject

Hardware and Architecture,Software

Reference37 articles.

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3. On design and application mapping of a Network-on-Chip (NoC) architecture;Bahn;Parallel Processing Letters,2008

4. S. Bell et al., TILE64 processor: a 64-core SoC with mesh interconnect, in: IEEE International Solid-State Circuits Conference on Performance Analysis of Systems and Software (ISPASS) Digest of Technical Papers, 2008, pp. 88–598.

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