A Survey of On-Chip Hybrid Interconnect for Multicore Architectures-Reference-Cited by-同舟云学术

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A Survey of On-Chip Hybrid Interconnect for Multicore Architectures

Published:2023 Issue: Volume: Page:59-75
ISSN:1867-8211
Container-title:Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering
language:
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Author:

Pham-Quoc Cuong

Publisher

Springer Nature Switzerland

Link

https://link.springer.com/content/pdf/10.1007/978-3-031-28816-6_5

Reference41 articles.

1. Avakian, A., et al.: A reconfigurable architecture for multicore systems. In: IPDPSW, pp. 1–8 (2010). https://doi.org/10.1109/IPDPSW.2010.5470753

2. Balfour, J., Dally, W.J.: Design tradeoffs for tiled CMP on-chip networks. In: Proceedings of the 20th Annual International Conference on Supercomputing, ICS 2006, pp. 187–198. ACM, New York (2006). https://doi.org/10.1145/1183401.1183430. http://doi.acm.org/10.1145/1183401.1183430

3. Balkan, A., Qu, G., Vishkin, U.: A mesh-of-trees interconnection network for single-chip parallel processing. In: International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2006, pp. 73–80 (2006). https://doi.org/10.1109/ASAP.2006.6

4. Balkan, A.O., Qu, G., Vishkin, U.: An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing. In: Proceedings of the 45th Annual Design Automation Conference, DAC 2008, pp. 435–440, ACM, New York (2008). https://doi.org/10.1145/1391469.1391583. http://doi.acm.org/10.1145/1391469.1391583

5. Bourduas, S., Zilic, Z.: Modeling and evaluation of ring-based interconnects for network-on-chip. J. Syst. Archit. 57(1), 39–60 (2011). https://doi.org/10.1016/j.sysarc.2010.07.002. http://www.sciencedirect.com/science/article/pii/S138376211000069X. Special Issue On-Chip Parallel and Network-Based Systems

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