A Mesh-of-Trees Interconnection Network for Single-Chip Parallel Processing-Reference-Cited by-同舟云学术

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A Mesh-of-Trees Interconnection Network for Single-Chip Parallel Processing

Published:2006 Issue: Volume: Page:
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Container-title:IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)
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Author:

Balkan Aydin,Qu Gang,Vishkin Uzi

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4019472/4019473/04019494.pdf?arnumber=4019494

Cited by 24 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Survey of On-Chip Hybrid Interconnect for Multicore Architectures;Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering;2023

2. A Many-Ported and Shared Memory Architecture for High-Performance ADAS SoCs;IEEE Design & Test;2022-12

3. Fault-Tolerant Application Mapping on Mesh-of-Tree based Network-on-Chip;Journal of Systems Architecture;2021-06

4. Meshed Bluetree: Time-Predictable Multimemory Interconnect for Multicore Architectures;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2020-11

5. Combinatorics and Geometry for the Many-ported, Distributed and Shared Memory Architecture;2020 14th IEEE/ACM International Symposium on Networks-on-Chip (NOCS);2020-09-24

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