Enhancing the Forward Gate Bias Robustness in p‐GaN Gate High‐Electron‐Mobility Transistors through Doping Profile Engineering

Abstract

This article presents a study on the improvement of the gate robustness and reliability of p‐GaN gate high‐electron‐mobility transistors (HEMTs) by doping profile engineering and by performing a thermal treatment. The reduction of the p‐doping concentration at the Schottky interface using a graded magnesium (Mg) profile in the p‐GaN layer and introducing a top Si‐GaN cap layer is proposed, combined with a high‐temperature anneal step after the gate patterning. The results show that the proposed approach enhances the gate breakdown voltage, reduces the gate leakage current, and increases the time to failure under constant voltage stress, while ensuring stable dynamic behavior and off‐state leakage performance under high‐voltage stress.