Reduction of the Hysteresis Voltage in Atomic‐Layer‐Deposited p‐Type SnO Thin‐Film Transistors by Adopting an Al 2 O 3 Interfacial Layer-Reference-Cited by-同舟云学术

Reduction of the Hysteresis Voltage in Atomic‐Layer‐Deposited p‐Type SnO Thin‐Film Transistors by Adopting an Al 2 O 3 Interfacial Layer

Published:2019-05-23 Issue:7 Volume:5 Page:1900371
ISSN:2199-160X
Container-title:Advanced Electronic Materials
language:en
Short-container-title:Adv. Electron. Mater.

Author:

Jang Younjin¹,Yeu In Won¹²,Kim Jun Shik¹,Han Jeong Hwan³,Choi Jung‐Hae²,Hwang Cheol Seong¹^ORCID

Affiliation:

1. Department of Materials Science and Engineering and Inter‐University Semiconductor Research CenterSeoul National University Gwanak‐ro 1 Gwanak‐gu Seoul 08826 Republic of Korea

2. Center for Electronic MaterialsKorea Institute of Science and Technology Hwarang‐ro 14‐gil 5 Seongbuk‐gu Seoul 02792 Republic of Korea

3. Department of Materials Science and EngineeringSeoul National University of Science and Technology Gongneung‐ro 232 Nowon‐gu Seoul 01811 Republic of Korea

Funder

Ministry of Trade, Industry and Energy

Korea Institute of Science and Technology

Publisher

Wiley

Subject

Electronic, Optical and Magnetic Materials

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1002/aelm.201900371

Reference45 articles.

1. Amorphous Oxide Semiconductor TFTs for Displays and Imaging

2. In2Ga2ZnO7oxide semiconductor based charge trap device for NAND flash memory