Design and analysis of ultra‐low power 18T adaptive data track flip‐flop for high‐speed application

Author:

Kumar Mishra Alok1ORCID,Vaithiyanathan Dhandapani1ORCID,Chopra Urvashi1

Affiliation:

1. National Institute of Technology Delhi Delhi India

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Low power and noise‐immune 9 T compute SRAM cell design based on differential power generator and Schmitt‐trigger logics with14 nm FinFET technology;International Journal of Circuit Theory and Applications;2024-06-27

2. Design and Analysis of Low-Power and Area-Efficient Master-Slave Flip-Flop;IETE Journal of Research;2024-05-21

3. Review of Dual-Edge Triggered Low-Power D Flip-Flops;2023 3rd International Conference on Smart Generation Computing, Communication and Networking (SMART GENCON);2023-12-29

4. Unleashing Power Efficiency: A Study Comparing Pulsed Latches and Flip-Flops for Low-Power Applications;2023 3rd International Conference on Smart Generation Computing, Communication and Networking (SMART GENCON);2023-12-29

5. Design and Analysis of 18T Master-Slave Flip-Flop Circuit;2023 12th International Conference on System Modeling & Advancement in Research Trends (SMART);2023-12-22

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