Author:
Biere Armin,Kunz Wolfgang
Cited by
7 articles.
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1. FPGA Design Deobfuscation by Iterative LUT Modification at Bitstream Level;Journal of Hardware and Systems Security;2023-02-16
2. Exploiting Reversible Computing for Verification;Proceedings of the 28th Asia and South Pacific Design Automation Conference;2023-01-16
3. Usage-Based RTL Subsetting for Hardware Accelerators;Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design;2022-10-30
4. Characteristics of reversible circuits for error detection;Array;2022-07
5. A General Equivalence Checking Framework for Multivalued Logic;Proceedings of the 26th Asia and South Pacific Design Automation Conference;2021-01-18