Author:
Chen Chunhong,Kang Changjun,Sarrafzadeh Majid
Cited by
5 articles.
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1. On optimal flip-flop grouping for VLSI power minimization;Operations Research Letters;2013-09
2. Agglomerative-based flip-flop merging and relocation for signal wirelength and clock tree optimization;ACM Transactions on Design Automation of Electronic Systems;2013-07
3. Clock Network Synthesis with Concurrent Gate Insertion;Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation;2011
4. Synthesis of clock and power/ground networks;Electronic Design Automation;2009
5. Low-power gated and buffered clock network construction;ACM Transactions on Design Automation of Electronic Systems;2008-01