On optimal flip-flop grouping for VLSI power minimization
Author:
Publisher
Elsevier BV
Subject
Applied Mathematics,Industrial and Manufacturing Engineering,Management Science and Operations Research,Software
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2. Optimal VLSI Delay Tuning by Space Tapering With Clock-Tree Application;IEEE Transactions on Circuits and Systems I: Regular Papers;2017-08
3. Easy and difficult exact covering problems arising in VLSI power reduction by clock gating;Discrete Optimization;2014-11
4. Using well-solvable minimum cost exact covering for VLSI clock energy minimization;Operations Research Letters;2014-07
5. A Look-Ahead Clock Gating Based on Auto-Gated Flip-Flops;IEEE Transactions on Circuits and Systems I: Regular Papers;2014-05
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