Synthesis of clock and power/ground networks-Reference-Cited by-同舟云学术

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Synthesis of clock and power/ground networks

Published:2009 Issue: Volume: Page:751-850
ISSN:
Container-title:Electronic Design Automation
language:
Short-container-title:

Author:

Koh Cheng-Kok,Jain Jitesh,Cauley Stephen F.

Publisher

Elsevier

Reference82 articles.

1. Circuits, Interconnections, and Packaging for VLSI;Bakoglu,1990

2. Introduction to Algorithms;Cormen,2001

3. Linear and Nonlinear Programming;Luenberger,2003

4. Digital Integrated Circuits: A Design Perspective;Rabaey,2003

5. Fundamentals of Microsystems Packaging;Rao,2001

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11

2. Synthesis and exploration of clock spines;IET Computers & Digital Techniques;2018-07-10

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