CLARA

Author:

Agrawal Aditya,O'Connor Mike,Bolotin Evgeny,Chatterjee Niladrish,Emer Joel,Keckler Stephen

Publisher

ACM

Reference50 articles.

1. 1 Gb GDDR5 SGRAM H5GQ1H24AFR. {Online}. Available: http://www.hynix.com/datasheet/pdf/graphics/H5GQ1H24AFR(Rev1.0).pdf 1 Gb GDDR5 SGRAM H5GQ1H24AFR. {Online}. Available: http://www.hynix.com/datasheet/pdf/graphics/H5GQ1H24AFR(Rev1.0).pdf

2. Micron DDR4 SDRAM. {Online}. Available: http://www.micron.com/products/dram/ddr4-sdram Micron DDR4 SDRAM. {Online}. Available: http://www.micron.com/products/dram/ddr4-sdram

3. Page Placement Strategies for GPUs within Heterogeneous Memory Systems

4. A. Agrawal A. Ansari and J. Torrellas "Mosaic: Exploiting the Spatial Locality of Process Variation to Reduce Refresh Energy in On-Chip eDRAM Modules " in International Symposium on High Performance Computer Architecture Feb. 2014. A. Agrawal A. Ansari and J. Torrellas "Mosaic: Exploiting the Spatial Locality of Process Variation to Reduce Refresh Energy in On-Chip eDRAM Modules " in International Symposium on High Performance Computer Architecture Feb. 2014.

5. Refrint: Intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Voltage Reduced Self Refresh (VRSR) for optimized energy savings in DRAM Memories;Memories - Materials, Devices, Circuits and Systems;2023-07

2. Per-bank refresh with adaptive early termination for high density DRAM;Proceedings of the 4th International Conference on Communication and Information Processing - ICCIP '18;2018

3. Using run-time reverse-engineering to optimize DRAM refresh;Proceedings of the International Symposium on Memory Systems;2017-10-02

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