Smart-Hop Arbitration Request Propagation

Author:

Asgarieh Yashar1,Lin Bill1

Affiliation:

1. University of California, San Diego, California

Abstract

SMART-based NoC designs achieve ultra-low latencies by enabling flits to traverse multiple hops within a single clock cycle. Notwithstanding the clear performance benefits, SMART-based NoCs suffer from several shortcomings: each router must arbitrate among a quadratic number of requests, which leads to high costs; each router independently makes its own arbitration decisions, which leads to a problem called false negatives that causes throughput loss. In this article, we propose a new SMART-based NoC design called SHARP that overcomes these shortcomings. Our evaluation demonstrates that SHARP increases throughput by up to 19% and average link utilization by up to 24% by avoiding false negatives. By avoiding quadratic arbitration, our evaluation further demonstrates that SHARP reduces the wiring and area overhead significantly.

Publisher

Association for Computing Machinery (ACM)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications

Cited by 14 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. DAG-Order: An Order-Based Dynamic DAG Scheduling for Real-Time Networks-on-Chip;ACM Transactions on Architecture and Code Optimization;2023-12-15

2. Scheduling Strategies and Future Directions for NoC: A Systematic Literature Review;Automatic Control and Computer Sciences;2023-08

3. PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs;Micromachines;2023-02-21

4. LAMP: Load-Balanced Multipath Parallel Transmission in Point-to-Point NoCs;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2022-12

5. SMT-Based Contention-Free Task Mapping and Scheduling on 2D/3D SMART NoC with Mixed Dimension-Order Routing;ACM Transactions on Architecture and Code Optimization;2022-03-31

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