Scheduling Strategies and Future Directions for NoC: A Systematic Literature Review
Author:
Publisher
Allerton Press
Subject
Signal Processing,Control and Systems Engineering,Software
Link
https://link.springer.com/content/pdf/10.3103/S0146411623040041.pdf
Reference22 articles.
1. Manokaran, J.P.R. and Khalid, M.A., Experimental evaluation and comparison of two recent Network-on-Chip routers for FPGAs, Microprocessors Microsystems, 2017, vol. 51, pp. 134–141. https://doi.org/10.1016/j.micpro.2017.04.008
2. Khan, A.A., Mir, R.N., and Najeeb, U., Fault-tolerant buffer aware round robin arbiter design for NoC architectures, Int. J. Comput. Digital Syst., 2019, vol. 8, no. 3, pp. 275–284. https://doi.org/10.12785/ijcds/080307
3. Fazel Zarandi, M.H., Sadat Asl, A.A., Sotudian, S., and Castillo, O., A state of the art review of intelligent scheduling, Artif. Intell. Rev., 2020, vol. 53, no. 1, pp. 501–593. https://doi.org/10.1007/s10462-018-9667-6
4. Zhang, Z., Gao, X., and Long, X., RARR: Reverse anchored round-robin for link scheduling in network-on-chip, 2008 Int. Conf. on Embedded Software and Systems Symposia, Chegndu, China, 2008, IEEE, 2008, pp. 318–323. https://doi.org/10.1109/icess.symposia.2008.14
5. Cai, X., Yin, J., and Zhou, P., An orchestrated NoC prioritization mechanism for heterogeneous CPU-GPU systems, Integration, 2019, vol. 65, pp. 344–350. https://doi.org/10.1016/j.vlsi.2018.04.005
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