GARNET: A detailed on-chip network model inside a full-system simulator-Reference-Cited by-同舟云学术

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GARNET: A detailed on-chip network model inside a full-system simulator

Published:2009-04 Issue: Volume: Page:
ISSN:
Container-title:2009 IEEE International Symposium on Performance Analysis of Systems and Software
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Author:

Agarwal Niket,Krishna Tushar,Peh Li-Shiuan,Jha Niraj K.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4907867/4919623/04919636.pdf?arnumber=4919636

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