Evaluation of Latch-based Physical Random Number Generator Implementation on 40 nm ASICs
Author:
Affiliation:
1. Fujitsu Laboratories Ltd., Kawasaki, Japan
2. Yokohama National University, Yokohama, Japan
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2995289.2995292
Reference30 articles.
1. T. Amaki M. Hashimoto and T. Onoye. A process and temperature tolerant oscillator-based true random number generator. IEICE Trans. Fundamentals E97-A(12):2393--2399 2014. T. Amaki M. Hashimoto and T. Onoye. A process and temperature tolerant oscillator-based true random number generator. IEICE Trans. Fundamentals E97-A(12):2393--2399 2014.
2. A low-power true random number generator using random telegraph noise of single oxide-traps
3. A high-speed ic random-number source for smartcard microcontrollers
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