MOESI-prime

Author:

Loughlin Kevin1,Saroiu Stefan2,Wolman Alec2,Manerkar Yatin A.1,Kasikci Baris1

Affiliation:

1. University of Michigan

2. Microsoft

Funder

NSF (National Science Foundation)

Google

Publisher

ACM

Reference121 articles.

1. Paul Alcorn. 2022. New UCIe Chiplet Standard Supported by Intel AMD and Arm. tomshardware.com/news/new-ucie-chiplet-standard-supported-by-intel-amd-and-arm. Paul Alcorn. 2022. New UCIe Chiplet Standard Supported by Intel AMD and Arm. tomshardware.com/news/new-ucie-chiplet-standard-supported-by-intel-amd-and-arm.

2. Spandex: A Flexible Interface for Efficient Heterogeneous Coherence

3. Hesham Altwaijry and Diyab S Alzahrani . 2014. Improved-moesi cache coherence protocol. Arabian Journal for Science and Engineering ( 2014 ). Hesham Altwaijry and Diyab S Alzahrani. 2014. Improved-moesi cache coherence protocol. Arabian Journal for Science and Engineering (2014).

4. Zelalem Birhanu Aweke , Salessawi Ferede Yitbarek , Rui Qiao, Reetuparna Das, Matthew Hicks, Yossi Oren, and Todd Austin. 2016 . ANVIL : Software-Based Protection Against Next-Generation Rowhammer Attacks. In ACM SIGARCH Computer Architecture News (CAN) . Zelalem Birhanu Aweke, Salessawi Ferede Yitbarek, Rui Qiao, Reetuparna Das, Matthew Hicks, Yossi Oren, and Todd Austin. 2016. ANVIL: Software-Based Protection Against Next-Generation Rowhammer Attacks. In ACM SIGARCH Computer Architecture News (CAN).

5. Christel Baier and Joost-Pieter Katoen . 2008. Principles of Model Checking (Representation and Mind Series) . The MIT Press . Christel Baier and Joost-Pieter Katoen. 2008. Principles of Model Checking (Representation and Mind Series). The MIT Press.

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1. MARF: A Memory-Aware CLFLUSH-Based Intra- and Inter-CPU Side-Channel Attack;Computer Security – ESORICS 2023;2024

2. Coherence Attacks and Countermeasures in Interposer-Based Chiplet Systems;ACM Transactions on Architecture and Code Optimization;2023-11-20

3. How to Kill the Second Bird with One ECC: The Pursuit of Row Hammer Resilient DRAM;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28

4. D-wash – A dynamic workload aware adaptive cache coherance protocol for multi-core processor system;Microelectronics Journal;2023-02

5. Scalable and Secure Row-Swap: Efficient and Safe Row Hammer Mitigation in Memory Systems;2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2023-02

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