SCAIE-V

Author:

Damian Mihaela1,Oppermann Julian1,Spang Christoph1,Koch Andreas1

Affiliation:

1. Technical University Darmstadt, Darmstadt, Germany

Funder

Bundesministerium für Bildung und Forschung

Publisher

ACM

Reference19 articles.

1. Codasip. 2021. Codasip. https://codasip.com/. Online ; accessed Sept. 2021 . Codasip. 2021. Codasip. https://codasip.com/. Online; accessed Sept. 2021.

2. Codasip. 2021. Codasip Tools. https://design-reuse.com/articles/46237/extending-risc-v-isa-with-a-custom-instruction-set-extension.html Online ; accessed Sept. 2021 . Codasip. 2021. Codasip Tools. https://design-reuse.com/articles/46237/extending-risc-v-isa-with-a-custom-instruction-set-extension.html Online; accessed Sept. 2021.

3. Div. 2021. Andes Custom extension. http://www.andestech.com/en/products-solutions/andes-custom-extension/ Div. 2021. Andes Custom extension. http://www.andestech.com/en/products-solutions/andes-custom-extension/

4. Div. 2021. ORCA Lightweight Vector Extensions. https://riscv.org/wp-content/uploads/2016/07/Tue1515_orca_lve.pdf. Online ; accessed Sept. 2021 . Div. 2021. ORCA Lightweight Vector Extensions. https://riscv.org/wp-content/uploads/2016/07/Tue1515_orca_lve.pdf. Online; accessed Sept. 2021.

5. Div. 2021. PicoRV32. https://github.com/cliffordwolf/picorv32. Online ; accessed Sept. 2021 . Div. 2021. PicoRV32. https://github.com/cliffordwolf/picorv32. Online; accessed Sept. 2021.

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Longnail: High-Level Synthesis of Portable Custom Instruction Set Extensions for RISC-V Processors from Descriptions in the Open-Source CoreDSL Language;Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3;2024-04-27

2. BlueFace: Integrating an Accelerator into the Core’s Pipeline through Algorithm-Interface Co-Design for Real-Time SoCs;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09

3. Bits, Flips and RISCs;2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS);2023-05-03

4. Prototyping Reconfigurable RRAM-Based AI Accelerators Using the RISC-V Ecosystem and Digital Twins;Lecture Notes in Computer Science;2023

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