1. Asanovic, K., et al.: The rocket chip generator. EECS Department, University of California, Berkeley, Technical report UCB/EECS-2016-17 4 (2016)
2. Asanović, K., Patterson, D.A.: Instruction sets should be free: the case for RISC-V. EECS Department, University of California, Berkeley, Technical report UCB/EECS-2014-146 (2014)
3. Damian, M., Oppermann, J., Spang, C., Koch, A.: SCAIE-V: an open-source scalable interface for ISA extensions for RISC-V processors. In: Proceedings of the 59th ACM/IEEE Design Automation Conference, pp. 169–174 (2022)
4. Lecture Notes in Computer Science;M Fritscher,2022
5. Greengard, S.: Will RISC-V revolutionize computing? Commun. ACM 63(5), 30–32 (2020)