Longnail: High-Level Synthesis of Portable Custom Instruction Set Extensions for RISC-V Processors from Descriptions in the Open-Source CoreDSL Language-Reference-Cited by-同舟云学术

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Longnail: High-Level Synthesis of Portable Custom Instruction Set Extensions for RISC-V Processors from Descriptions in the Open-Source CoreDSL Language

Published:2024-04-27 Issue: Volume:2023 Page:591-606
ISSN:
Container-title:Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3
language:
Short-container-title:

Author:

Oppermann Julian¹^ORCID,Damian-Kosterhon Brindusa Mihaela¹^ORCID,Meisel Florian¹^ORCID,Mürmann Tammo¹^ORCID,Jentzsch Eyck²^ORCID,Koch Andreas¹^ORCID

Affiliation:

1. Technical University of Darmstadt, Darmstadt, Germany

2. MINRES Technologies GmbH, Neubiberg, Germany

Funder

Federal Ministry of Education and Research

Publisher

ACM

Reference55 articles.

1. A FPGA friendly 32 bit RISC-V CPU implementation. https://github.com/SpinalHDL/VexRiscv.

2. Language engineering for everyone. https://eclipse.dev/Xtext/.

3. Mirror of the now discontinued ORCA RISC-V processor from Vector-Blox. https://github.com/cahz/orca.

4. PicoRV32 - A Size-Optimized RISC-V CPU. https://github.com/YosysHQ/picorv32.

5. RISC-V CPU simple 3-stage pipeline for low-end applications. https://github.com/bluespec/Piccolo.

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