Author:
Janapsatya Andhi,Ignjatović Aleksandar,Parameswaran Sri
Cited by
8 articles.
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1. Switchable cache: utilising dark silicon for application specific cache optimisations;IET Computers & Digital Techniques;2016-07
2. Optimizing Performance of L1 Cache Memory for Embedded Systems driven by Differential Evolution;Proceedings of the Companion Publication of the 2015 Annual Conference on Genetic and Evolutionary Computation;2015-07-11
3. Design Space Exploration of L1 Data Caches for FPGA-Based Multiprocessor Systems;Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays;2015-02-22
4. A survey on cache tuning from a power/energy perspective;ACM Computing Surveys;2013-06
5. A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2013