A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches
Author:
Affiliation:
1. Dept. of Computer Science and Engineering, Waseda University
2. Dept. of Electronic and Photonic Systems, Waseda University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing
Link
https://www.jstage.jst.go.jp/article/transfun/E96.A/6/E96.A_1283/_pdf
Reference17 articles.
1. [1] W. Fornaciari, D. Sciuto, C. Silvano, and V. Zaccaria, “A design framework to efficiently explore energy-delay tradeoffs,” Proc. CODES 2001, pp.260-265, 2001.
2. [2] M.S. Haque, A. Janapsatya, and S. Parameswaran, “SuSeSim: A fast simulation strategy to find optimal L1 cache configuration for embedded systems,” Proc. CODES+ISSS 2009, pp.295-304, 2009.
3. [3] M.S. Haque, J. Peddersen, A. Janapsatya, and S. Parameswaran, “DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy,” Proc. DATE 2010, pp.496-501, 2010.
4. [4] M.S. Haque, J. Peddersen, A. Janapsatya, and S. Parameswaran, “SCUD: A fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy,” Proc. DAC 2010, pp.356-361, 2010.
5. [5] M.S. Haque, J. Peddersen, and S. Parameswaran, “CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique,” Proc. ICCAD 2011, pp.126-133, 2011.
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