Switchable cache: utilising dark silicon for application specific cache optimisations
Author:
Affiliation:
1. School of Computer Science and EngineeringUniversity of New South WalesSydneyAustralia
2. Google Inc.Mountain ViewCAUSA
3. Department of Computer EngineeringUniversity of PeradeniyaPeradeniyaSri Lanka
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2015.0114
Reference22 articles.
1. Taylor M.B.: ‘Is Dark Silicon Useful? harnessing the four horsemen of the coming dark silicon apocalypse’.Proc. of the Design Automation Conf. – (DAC'12) 2012 pp.1131–1136
2. Cong J. Xiao B.: ‘Optimization of interconnects between accelerators and shared memories in dark silicon’.Proc. of the IEEE/ACM Int. Conf. on Computer Aided Design (ICCAD'13) 2013
3. Accelerator memory reuse in the dark silicon era;Cota E.G.;Comput. Archit. Lett.,2014
4. Turakhia Y. Raghunathan B. Garg S. et al.: ‘HaDeS: architectural synthesis for heterogeneous dark silicon chip multi‐processors’.Proc. 50th Annual ACM/EDAC/IEEE Design Automation Conf. (DAC'13) 2013
5. Tuning Caches to Applications for Low-Energy Embedded Systems
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. An Overview of Design Space Exploration of Cache Memory;Proceedings of the 2nd International Symposium on Computer Science and Intelligent Control;2018-09-21
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