Design Space Exploration of L1 Data Caches for FPGA-Based Multiprocessor Systems-Reference-Cited by-同舟云学术

Design Space Exploration of L1 Data Caches for FPGA-Based Multiprocessor Systems

Published:2015-02-22 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
language:
Short-container-title:

Author:

Matthews Eric¹,Doyle Nicholas C.¹,Shannon Lesley¹

Affiliation:

1. Simon Fraser University, Burnaby, BC, Canada

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2684746.2689083

Reference14 articles.

1. Modular multi-ported SRAM-based memories

2. Aeroex Gaisler. GRLIB IP Core User's Manual. www.gaisler.com/products/grlib/grip.pdf. Aeroex Gaisler. GRLIB IP Core User's Manual. www.gaisler.com/products/grlib/grip.pdf.

3. Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite

4. Altera Corporation. Nios II Core Implementation Details Nios II Processor Reference Handbook. www.altera.com/literature/hb/nios2/nc2cpunii51015.pdf. Altera Corporation. Nios II Core Implementation Details Nios II Processor Reference Handbook. www.altera.com/literature/hb/nios2/nc2cpunii51015.pdf.

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Multipurpose Cacheing to Accelerate OpenMP Target Regions on FPGAs;OpenMP: Advanced Task-Based, Device and Compiler Programming;2023

2. Array-Specific Dataflow Caches for High-Level Synthesis of Memory-Intensive Algorithms on FPGAs;IEEE Access;2022

3. (FPL 2015) Scavenger;ACM Transactions on Reconfigurable Technology and Systems;2017-06-30

4. Automatic Construction of Program-Optimized FPGA Memory Networks;Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays;2017-02-22

5. Acceleration by Inline Cache for Memory-Intensive Algorithms on FPGA via High-Level Synthesis;IEEE Access;2017