A Methodology to Recover RTL IP Functionality for Automatic Generation of SW Applications

Author:

Bombieri Nicola1,Fummi Franco2,Vinco Sara3

Affiliation:

1. Università di Verona

2. EDALab s.r.l., Italy

3. Politecnico di Torino

Abstract

With the advent of heterogeneous multiprocessor system-on-chips (MPSoCs), hardware/software partitioning is again on the rise both in research and in product development. In this new scenario, implementing intellectual-property (IP) blocks as SW applications rather than dedicated HW is an increasing trend to fully exploit the computation power provided by the MPSoC CPUs. On the other hand, whole libraries of IP blocks are available as RTL descriptions, most of them without a corresponding high-level SW implementation. In this context, this article presents a methodology to automatically generate SW applications in C++, by starting from existing RTL IPs implemented in hardware description language (HDL). The methodology exploits an abstraction algorithm to eliminate implementation details typical of HW descriptions (such as cycle-accurate functionality and data types) to guarantee relevant performance of the generated code. The experimental results show that, in many cases, the C++ code automatically generated in a few seconds with the proposed methodology is as efficient as the corresponding code manually implemented from scratch.

Funder

EC co-funded SMAC

Publisher

Association for Computing Machinery (ACM)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications

Reference32 articles.

1. ALDEC. 2014. HES-DVM. http://aldec.com (2014). ALDEC. 2014. HES-DVM. http://aldec.com (2014).

2. Abstraction of RTL IPs into embedded software

3. Towards Equivalence Checking Between TLM and RTL Models

4. Carbon Design Systems. 2014. Carbon Model Studio. http://carbondesignsystems.com/. Carbon Design Systems. 2014. Carbon Model Studio. http://carbondesignsystems.com/.

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