VeriIntel2C: Abstracting RTL to C to maximize High-Level Synthesis Design Space Exploration-Reference-Cited by-同舟云学术

VeriIntel2C: Abstracting RTL to C to maximize High-Level Synthesis Design Space Exploration

Author:

Mahapatra Anushree^ORCID,Schafer Benjamin Carrion

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference25 articles.

1. I. T. R. For Semiconductors,2013

2. High-level Synthesis: from Algorithm to Digital Circuit;Coussy,2008

3. High-level synthesis for fpgas: from prototyping to deployment;Cong;IEEE Trans. Comput. Aided Des. Integrated Circ. Syst.,2011

4. Machine-learning based simulated annealer method for high level synthesis design space exploration;Mahapatra,2014

5. A method to abstract rtl ip blocks into c++ code and enable high-level synthesis;Bombieri,2013

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