Modernizing Hardware Circuits through High-Level Synthesis
Author:
Affiliation:
1. The University of Texas at Dallas,Department of Electrical and Computer Engineering,TX,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937493.pdf?arnumber=9937493
Reference18 articles.
1. VeriIntel2C: Abstracting RTL to C to maximize High-Level Synthesis Design Space Exploration
2. Optimizing RTL to C Abstraction Methodologies to Improve HLS Design Space Exploration
3. Verific Parser Platform,2021
4. Effective High-Level Synthesis Design Space Exploration through a Novel Cost Function Formulation
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. CERTIFY: AutomatiC MEasuRing The QualIty oF High-Level SYnthesis;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
2. MIRROR: MaxImizing the Re-usability of RTL thrOugh RTL to C CompileR;2023 Design, Automation & Test in Europe Conference & Exhibition (DATE);2023-04
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